1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a silicon on insulator (hereinafter simply referred to as "SOI") structure capable of achieving a high integration, and a manufacturing method thereof.
2. Description of the Prior Art
As shown in a CMOS device in which an element is formed in a well of a semiconductor wafer, a positive parasitic effect of a parasitic MOS transistor or a parasitic bipolar transistor is generated from a P-N junction separating structure. As a result, a latch-up phenomenon is generated whereby the device is destroyed or a soft error is generated.
In order to solve the foregoing problems and to accomplish a high integration, a semiconductor device having a SOI structure has been developed. In the SOI structure, a insulating layer is formed on a semiconductor substrate and a semiconductor layer is formed on the insulating layer. On the semiconductor layer, elements can be formed at predetermined regions. The semiconductor substrate is isolated from the regions by the insulating layer. Thereby, it is possible to completely separate the elements and to operate the semiconductor device at high speeds.
FIG. 1 is a sectional view of a conventional MOS transistor having a SOI structure. As shown in FIG. 1, by forming a insulating layer 2 and a semiconductor layer 3 on a semiconductor wafer 1 in sequence, a semiconductor substrate having the SOI structure is formed. Field oxidation films 4 are formed on the semiconductor layer 3. A gate insulating film 5 and a gate 6 are formed on the semiconductor layer 3 between the field oxidation films 4. A source region 7a and a drain region 7b are formed in the semiconductor layer 3. A intermediate Insulating layer 8 have contact holes for exposing predetermined portions of the source region 7a and the drain region 7b. In addition, a source electrode 9a and a drain electrode 9b are formed on the intermediate insulating layer 8. The source electrode 9a and the drain electrode 9b are brought into contact with the source region 7a and the drain region 7b through the contact holes.
In the MOS transistor having the SOI structure as described above, the source electrode 9a or the drain electrode 9b, an individual source or an individual drain of other MOS transistors are connected with a VSS or a VDD through a separate interconnection line.
Since density of the interconnections increases according to the high integration of the semiconductor device, the VSS or the VDD interconnection line is an obstacle to achieving high integration.